FIELD OF THE INVENTION
The present invention relates to a frame phase aligner which synchronously outputs the input data having different time deviations according to the reference frame signal.
Referring to FIG. 1 which shows a configuration of a conventional digital transfer system, a high speed receiver unit 1 receives and demultiplexes high speed serial data, and outputs a low speed parallel through-data group, clock and frame synchronous signal groups. A tributary interface unit 3 receives asynchronous data signal-3 As-3 and performs signal processing for DS-3 and then outputs an add-data group, clock and frame synchronous signal groups. These through-data and add-data groups and clock and frame synchronous signal groups will be selected, at a high speed signal transmitter unit 2, by a simple 2:1 selection method, and subsequently will be multiplexed in the form of high speed serial data.
The through-data and add-data, and clock and frame synchronous signals are to have time deviations in the view point of their arrival time at a high speed transmitter unit 2. In the case where big time deviations occur, these signals can not be synchronized and multiplexed correctly, that is, failures and errors in transferring data, which are detrimental obstructing factors to digital transport systems, can occur.
In other words, in the case where a multiplexing circuit used in the above synchronous digital transport systems distributes frame-synchronous signals and then receives back digital signals which are frame-synchronized to the distributed signals, the signals received back should in phase with each other, frame phase as well as bit phase. Due to variations in the delay time of passive components such as the length of pattern of signal flows and those of digital active components, the signals received back are to have time deviations. Accordingly, the digital transport system must clear these time deviations to correct retiming for arriving signals.